The use of nonvolatile memory devices has been increasing over recent years. These devices can retain data even while no power is applied. Memory cells of nonvolatile memory devices can typically be divided into a NAND-type memory cell and a NOR-type memory cell. The NAND-type memory cell has the advantage of high integration while the NOR-type memory cell has the advantage of high speed. This enables use of the two kinds of memory cells depending on an application's required advantage.
In the NOR-type nonvolatile memory device, a plurality of memory cells, each of which includes a single transistor, are connected in parallel to one bit line. Only one memory cell transistor is arranged between a drain connected to the bit line and a source connected to a common source line. The NOR-type nonvolatile memory device includes a high current memory cell and may operate at high speed. However, the nonvolatile memory device of NOR-type is improper for high-integration because the bit line contact and source line consume a relatively large amount of semiconductor area.
Furthermore, in the event that a threshold voltage of a memory cell transistor falls below a certain voltage (typically 0V) applied to a control gate electrode of the memory cell transistor, a current flows between a source and a drain regardless of on/off state of a voltage applied to the gate of the transistor. Such a memory cell is thus read to be in the on-state, and a misoperation occurs. Accordingly, the nonvolatile memory device requires strict control of the threshold voltage.
To solve the foregoing problems, nonvolatile memory devices of different structures, normally called “split-gate type”, have been proposed. A typical example of a split-gate type nonvolatile memory device is found in U.S. Pat. No. 5,045,488 entitled “METHOD OF MANUFACTURING A SINGLE TRANSISTOR NONVOLATILE, ELECTRICALLY ALTERABLE SEMICONDUCTOR MEMORY DEVICE”.
FIG. 1 is a schematic cross-sectional view of a prior art, split-gate type nonvolatile memory device, and FIG. 2 is a circuit diagram showing a portion of a cell array of the prior art split gate type nonvolatile memory device.
Referring to FIG. 1, the prior art split-gate type nonvolatile memory device includes a common source region CSL formed in a predetermined portion of an active region of a semiconductor substrate 100 and a pair of floating gates 104a disposed on the semiconductor substrate on either side of the source region CSL. A top surface of each floating gate 104a is covered with an elliptical oxide layer 108. A control gate electrode WL is disposed on the semiconductor substrate 100 adjacent to each floating gate 104a, and extends from a sidewall of the floating gate 104a to cover a portion of a top surface of the elliptical oxide layer 108. The control gate electrodes WL for the pair of floating gates 104a are formed on opposite sides of the floating gates 104a. Namely, as shown in FIG. 1, the device is symmetrical about the source region CSL.
A drain region 128d is disposed in the semiconductor substrate 100 adjacent to each control gate electrode WL. A portion of each drain region 128d extends under an associated control gate electrode WL. A first gate insulation layer 102 is formed between the floating gate 104a and the semiconductor substrate 100. A second gate insulation layer is formed over the semiconductor substrate between the control gate electrode WL and the semiconductor substrate 100. The second gate insulation layer includes a tunnel insulation layer 112, which covers the floating gate 104a, and a first gate insulation layer 102, which is formed under the floating gate 104a. A bit line plug BC is connected to the drain regions 128d (connection not shown in FIG. 1).
In a write mode, when a high voltage of 12V or higher is applied to the source region CSL and an appropriate voltage is applied to the drain region 128d and a control gate electrode WL, hot electrons pass through the first gate insulation layer 102 and are injected into the floating gate 104a from the semiconductor substrate under the floating gate 104a adjacent to the control gate electrode WL. In an erase mode, if a voltage of 15V or higher is applied to the control gate electrode WL, a high electric field is applied to a tip T of the floating gate electrode 104a. Thus, the electrons are emitted from the floating gate 104a to the control gate electrode WL.
Referring to FIG. 2, a cell array of the prior art nonvolatile memory comprises a plurality of split-gate type cells disposed in a matrix. Memory cells in each column share a control gate electrode WL or line and a common source region CSL. Memory cells in a row have drain regions connected to a same bit line BL. Pairs of columns of memory cells are connected to a same common source line.
As discussed above, a memory cell is programmed by applying a high voltage, for example, 12V or higher, to the source region CSL. Typically a low voltage of about zero volts is applied to the drain region 128d and a relatively low voltage of about one volt is applied to the control gate electrode WL. Electrons generated by the source region CSL will flow from the source region CSL toward the drain region 128d through a weakly inverted channel underneath the control gate electrode WL. When the electrons reach the region where the control gate electrode WL meets the sidewall of the floating gate 104a, the electrons see a steep potential drop approximately equal to the drain voltage. The electrons will accelerate and become heated and some of them will be injected into the floating gate 104a through the first gate insulation layer 102. However, because numerous memory cells share the same source region, and not all of those memory cells are selected for programming, voltages are applied, if possible, to the control gate electrode WL and drain regions 128d of those unselected memory cells to prevent programming of the unselected memory cells. Unfortunately, during the programming process described above with respect to the selected memory cells, unwanted tunneling and programming of unselected memory cells can still occur. Furthermore, as the number of memory cells connected to a common source region CSL increases, the undesired tunneling and programming of unselected memory cells takes place more frequently. As a result, this unwanted tunneling effect has placed a limit on the number of memory cells which can be connected to a common source line CSL, and memory devices require the formation of more separated common source regions CSL.